Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
CIOS ¸ù°í¸Þ¸® ¸ðµâ·¯ °ö¼À ¾Ë°í¸®Áò ±â¹Ý Scalable RSA °ø°³Å° ¾ÏÈ£ ÇÁ·Î¼¼¼ |
¿µ¹®Á¦¸ñ(English Title) |
Scalable RSA public-key cryptography processor based on CIOS Montgomery modular multiplication Algorithm |
ÀúÀÚ(Author) |
Á¶¿í·¡
½Å°æ¿í
Wook-Lae Cho
Kyung-Wook Shin
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¿ø¹®¼ö·Ïó(Citation) |
VOL 22 NO. 01 PP. 0100 ~ 0108 (2018. 01) |
Çѱ۳»¿ë (Korean Abstract) |
512/1,024/2,048/3,072 ºñÆ®ÀÇ 4°¡Áö Å° ±æÀ̸¦ Áö¿øÇÏ´Â scalable RSA °ø°³Å° ¾ÏÈ£ ÇÁ·Î¼¼¼¸¦ ¼³°èÇÏ¿´´Ù. RSA ¾ÏÈ£ÀÇ ÇÙ½É ¿¬»êºí·ÏÀÎ ¸ðµâ·¯ °ö¼À±â¸¦ CIOS (Coarsely Integrated Operand Scanning) ¸ù°í¸Þ¸® ¸ðµâ·¯ °ö¼À ¾Ë°í¸®µëÀ» ÀÌ¿ëÇÏ¿© 32 ºñÆ® µ¥ÀÌÅÍ Æнº·Î ¼³°èÇÏ¿´À¸¸ç, ¸ðµâ·¯ Áö¼ö½Â ¿¬»êÀº Left-to-Right (L-R) ÀÌÁø ¸è½Â ¾Ë°í¸®µëÀ» Àû¿ëÇÏ¿© ±¸ÇöÇÏ¿´´Ù. ¼³°èµÈ RSA ¾ÏÈ£ ÇÁ·Î¼¼¼¸¦ Virtex-5 FPGA·Î ±¸ÇöÇÏ¿© Çϵå¿þ¾î µ¿ÀÛÀ» °ËÁõÇÏ¿´À¸¸ç, 512/1,024/2,048/3,072 ºñÆ®ÀÇ Å° ±æÀÌ¿¡ ´ëÇØ °¢°¢ 456,051/3,496,347/26,011,947/88,112,770 Ŭ·Ï »çÀÌŬÀÌ ¼Ò¿äµÈ´Ù. 0.18 § CMOS Ç¥Áؼ¿ ¶óÀ̺귯¸®¸¦ »ç¿ëÇÏ¿© 100 MHz µ¿ÀÛ ÁÖÆļö·Î ÇÕ¼ºÇÑ °á°ú, 10,672 GE¿Í 6¡¿3,072 ºñÆ®ÀÇ ¸Þ¸ð¸®·Î ±¸ÇöµÇ¾ú´Ù. ¼³°èµÈ RSA °ø°³Å° ¾ÏÈ£ ÇÁ·Î¼¼¼´Â ÃÖ´ë µ¿ÀÛ ÁÖÆļö´Â 147 MHz·Î ¿¹ÃøµÇ¾úÀ¸¸ç, Å° ±æÀÌ¿¡ µû¶ó RSA º¹È£ ¿¬»ê¿¡ 3.1/23.8/177/599.4 ms °¡ ¼Ò¿äµÇ´Â °ÍÀ¸·Î Æò°¡µÇ¾ú´Ù.
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¿µ¹®³»¿ë (English Abstract) |
This paper describes a design of scalable RSA public-key cryptography processor supporting four key lengths of 512/1,024/ 2,048/3,072 bits. The modular multiplier that is a core arithmetic block for RSA crypto-system was designed with 32-bit datapath, which is based on the CIOS (Coarsely Integrated Operand Scanning) Montgomery modular multiplication algorithm. The modular exponentiation was implemented by using L-R binary exponentiation algorithm. The scalable RSA crypto- processor was verified by FPGA implementation using Virtex-5 device, and it takes 456,051/3,496347/26,011,947/88,112,770 clock cycles for RSA computation for the key lengths of 512/1,024/2,048/3,072 bits. The RSA crypto-processor synthesized with a 0.18§ CMOS cell library occupies 10,672 gate equivalent (GE) and a memory bank of 6¡¿3,072 bits. The estimated maximum clock frequency is 147 MHz, and the RSA decryption takes 3.1/23.8/177/599.4 msec for key lengths of 512/1,024/2,048/3,072 bits.
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Å°¿öµå(Keyword) |
RSA
°ø°³Å° ¾ÏÈ£
¸ù°í¸Þ¸® ¸ðµâ·¯ °ö¼À ¾Ë°í¸®µë
¸ðµâ·¯ °ö¼À±â
CIOS
RSA
public-key cryptography
Montgomery modular multiplication algorithm
modular multiplier
CIOS
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ÆÄÀÏ÷ºÎ |
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